Education

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• 1987 Ph.D., University of California, Santa Barbara, USA 
• 1985 M.S., University of California, Santa Barbara, USA
• 1981 B.S., National Taiwan University, Taiwan, R.O.C

Background

• 2007-present General Director, SoC Technology Center, Industrial Technology Research Institute
• 2004-2007 Dean, College of Electrical Engineering & Computer Science, NTHU
• 2006-2007 Director, National SOC Program, NSC
• 2005-2006 Chair, Steering Committee of the Asian Test Symposium
• 2003-2005 Chair, Technical Meetings Group, TTTC, IEEE Computer Society
• 2003-2007 Consultant, SOC Technology Center, ITRI, Hsinchu, Taiwan
• 2002-present Member, BOG of Taiwan IC Design Society
• 2000-2006 Member, BOG of IEEE Taipei Section
• 2000-2004 Director, IC Design Technology Center (DTC), NTHU
• 2000-2003 Chair, Department of EE, NTHU
• 1999-2000 Visiting Researcher, Department of ECE, UCSB
• 1998-1999 Director, Technology Service Center, National Tsing Hua University, Hsinchu, Taiwan
• 1998-2003 Consultant, Global UniChip Co., Science Park, Hsinchu, Taiwan (Embedded DRAM Testing and Diagnosis)
• 1996-1998 Director, Computer & Communications Center, National Tsing Hua University, Hsinchu, Taiwan
• 1994-present Professor, Dept. EE, National Tsing Hua University, Hsinchu, Taiwan
• 1995 Consultant, Faraday Technology Co., Science Park, Hsinchu, Taiwan (Memory Testing)
• 1994 Consultant, Computer & Communication Research Labs, ITRI, Hsinchu, Taiwan (Design for Testability)
• 1992-1994 Consultant, Syntest Co., Science Park, Hsinchu, Taiwan (Boundary Scan Conformance Test)
• 1990-1993 Adjunct Associate Prof., Feng Chia University, Taichung, Taiwan
• 1991-1992 Adjunct Associate Prof., Chung Hua Inst. Technology, Hsinchu, Taiwan
• 1990-1991 Consultant, Telecommunications Labs., Chungli, Taiwan (Design for Testability)
• 1988-1994 Associate Professor, Dept. EE, National Tsing Hua University, Hsinchu, Taiwan
• 1987-1988 Post Graduate Researcher, University of California, Santa Barbara
• 1985-1987 Research Assistant, University of California, Santa Barbara 
• 1984-1985 Teaching Assistant, University of California, Santa Barbara
• 1983-1984 Systems Programmer, Bureau of Environmental Protection, Taipei, Taiwan
• 1983-1984 Adjunct Lecturer, Jing Hua Computer Training School, Taipei, Taiwan 
• 1981-1983 Ensign Instructor, Naval School of Communications & Electronics, Kaohsung, Taiwan 

Research Interests

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IC design and test; memory test and repair

Honors

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• 2007 Industrial Collaboration Award, NTHU
• 2007 VTS Best Innovative Practices Session Award, IEEE Computer Society
• 2006 Tsing Hua Chair Professor, NTHU
• 2006 Distinguished Teaching Award, NTHU
• 2006 Golden Core Member, the IEEE Computer Society
• 2005 Outstanding Contribution Award, the IEEE Computer Society
• 2005 Continuous Service Award, the IEEE Computer Society
• 2005 Academic Award, the Ministry of Education
• 2004 Fellow, the IEEE
• 2003 Special Feature Award, University Design Contest, the IEEE Asia & South Pacific Design Automation Conference (ASP-DAC)
• 2003 Best Paper Award, the IEEE Asia & South Pacific Design Automation Conference (ASP-DAC)
• 2002 Best Paper Award, the IEEE International Workshop on Design & Diagnostics of Electronic Circuits & Systems
• 2001 Industrial Collaboration Award, the Ministry of Education
• 2000 and 2002 Distinguished Research Awards, the National Science Council
• 1997, 2001, 2003, and 2006 Certificates of Appreciation for dedicated service to the Asian Test Symposium and TTTC, the IEEE Computer Society
• 1997 Outstanding Electrical Engineering Professor Award, the Chinese Institute of Electrical Engineering
• 1996 Distinguished Teaching Award, National Tsing Hua University (NTHU)

 Recent Publications

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• Chin-Lung Su; Chih-Wea Tsai; Cheng-Wen Wu; Chien-Chung Hung; Young-Shying Chen; Ding-Yeong Wang; Yuan-Jen Lee; Ming-Jer Kao; Write Disturbance Modeling and Testing for MRAM, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 16, Issue 3, March 2008 Page(s): 277 - 288 
• Rei-Fu Huang, Chao-Hsun Chen, Cheng-Wen Wu, Economic Aspects of Memory Built-in Self-Repair, IEEE Design and Test of Computers, Volume 24, Issue 2, pp. 164-173, March 2007.
• C.-Y. Lo, C.-H. Wang, K.-L. Cheng, J.-R. Huang, C.-W. Wang, S.-M. Wang, and C.-W, Wu, STEAC: A Platform for Automatic SOC Test Integration, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 15, Issue 5, Page(s): 541–545, May 2007.
• J.-C. Yeh, K.-L. Cheng, Y.-F. Chou, C.-W. Wu, Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 26, Issue: 6, pp. 1101-1113, June 2007.
• Jin-Fu Li; Yeh, J.-C.; Rei-Fu Huang; Cheng-Wen Wu; A built-in self-repair design for RAMs with 2-D redundancy IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 13, Issue 6, June 2005 Page(s):742 - 745
• Shyue-Kung Lu; Yu-Chen Tsai; Hsu, C.-H.; Kuo-Hua Wang; Cheng-Wen Wu; Efficient built-in redundancy analysis for embedded memories with 2-D redundancy, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 14, Issue 1, Jan. 2006, Page(s):34 - 42
• J.-F. Li, J.-C. Yeh, R.-F. Huang, and C.-W. Wu, A built-in self-repair design for RAMs with 2-D redundancy, IEEE Trans. on VLSI Systems, vol. 13, no. 6, pp. 742{745, June 2005.
• Rei-Fu Huang; Jin-Fu Li; Jen-Chieh Yeh; Cheng-Wen Wu; Raisin: Redundancy Analysis Algorithm Simulation, IEEE Design & Test of Computers, Volume 24, Issue 4, July-Aug. 2007 Page(s): 386 - 396
• J.-C. Yeh, S.-F. Kuo, C.-H. Chen, and C.-W. Wu, A systematic approach to memory test time reduction, IEEE Design & Test of Computers, 2007 (accepted).
• Y.-L. Peng, J.-J. Liou, C.-T. Huang, and C.-W. Wu, BIST-based diagnosis scheme for FPGA interconnect delay faults, IET Computers & Digital Techniques, Vol. 1, No. 6, Nov. 2007 (to appear), pp. 716-723.
• C.-W. Wu, SOC testing methodology and practice", in Proc. Conf. Design, Automation, and Test in Europe (DATE), Munich, Mar. 2005, pp. 1120-1121.
• J.-C. Yeh, Y.-T. Lai, Y.-Y. Shih, and C.-W. Wu, Flash memory built-in self-diagnosis with test mode control, in Proc. IEEE VLSI Test Symp. (VTS), Palm Springs, May 2005, pp. 15-20.
• C.-C. Wang, J.-J. Liou, Y.-L. Peng, C.-T. Huang, and C.-W. Wu, A BIST scheme for FPGA interconnect delay faults, in Proc. IEEE VLSI Test Symp. (VTS), Palm Springs, May 2005, pp. 201-206.
• C.-H. Wang, J.-C. Yeh, C.-T. Huang, and C.-W. Wu, Scalable security processor design and its implementation, in Proc. IEEE Asian Solid-State Circuit Conf. (A-SSCC), Hsinchu, Nov. 2005, pp. 513-516.
• Y.-Y. Hsiao, C.-H. Chen, and C.-W. Wu, A built-in self-repair scheme for NOR-type flash memory, in Proc. IEEE VLSI Test Symp. (VTS), Berkeley, Apr. 2006, pp. 114-119.
• C.-H. Wang, C.-Y. Lo, M.-S. Lee, J.-C. Yeh, C.-T. Huang, C.-W. Wu, and S.-Y. Huang, A network security processor design based on an integrated SOC design and test platform", in Proc. IEEE/ACM Design Automation Conf. (DAC), San Francisco, July 2006.
• C.-L. Su, C.-W. Tsai, C.-W. Wu, C.-C. Hung, Y.-S. Chen, and M.-J. Kao, Testing MRAM for write disturbance fault, in Proc. Int'l Test Conf. (ITC), Santa Clara, Oct. 2006.
• B.-Y. Chen, Y.-T. Yeh, C.-H. Chen, J.-C. Yeh, C.-W. Wu, J.-S. Lee, and Y.-C. Lin, An enhanced edac methodology for low power PSRAM, in Proc. Int'l Test Conf. (ITC), Santa Clara, Oct. 2006.
• L.-M. Denq, T.-C. Wang, and C.-W. Wu, ``An enhanced SRAM BISR design with reduced timing penalty'', in Proc. 15th IEEE Asian Test Symp. (ATS), Fukuoka, Japan, Nov. 2006.
• Y.-T. Hsing, C.-C. Huang, J.-C. Yeh, and C.-W. Wu, SDRAM delay fault modeling and performance testing, in Proc. IEEE VLSI Test Symp. (VTS), Berkeley, May 2007, pp. 53-58.
• C.-L. Su, C.-W. Tsai, C.-W. Wu, J.-J. Chen, W.-C. Wu, C.-C. Hung, and M.-J. Kao, Diagnosis for MRAM write disturbance fault, in Proc. Int'l Test Conf. (ITC), Santa Clara, Oct. 2007.
• Hsiang-Huang Wu, Jin-Fu Li, Chi-Feng Wu, and Cheng-Wen Wu, "CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMs", in Proc. IEEE 16th Asian Test Symposium (ATS), Oct. 2007, pp. 355 - 360.
• Li-Ming Denq and Cheng-Wen Wu, "A Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories", in Proc. IEEE 16th Asian Test Symposium (ATS), Oct. 2007, pp. 349 - 354.
• Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Hsi-Pin Ma, Ying-Yen Chen, Yueh-Chih Hsu, Li-Ming Deng, Chien-Jung Chiu, Young-Wey Li, and Chieh-Ming Chang, "A prototype of a wireless-based test system", in Proc. IEEE International SOC Conference, Sept. 2007, Page(s): 225-228.
• Yu-Tsao Hsing, Song-Guang Wu, and Cheng-Wen Wu, "RAMSES-D: DRAM fault simulator supporting weighted coupling fault", in Proc. IEEE Memory Technology, Design and Testing Workshop (MTDT), Dec. 2007, Page(s): 33-38. 

Professional Activities

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Patents

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Public Speeches

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Is Multi-Thousand-Core Processor Foreseeable?
EDA Development Forum 2008
Grand Formosa Regent
May 7, 2008, Taipei, Taiwan

What do you care about future test research? What do they care anyway?
VLSI Test Technology Workshop（VTTW）
Evergreen Plaza Hotel
July 16-18, 2008, Tainan, Taiwan