Technology Overview
The software solutions for the AI chip design contain “the static performance analysis technology”, “the full-system virtual platform”and “the compiler optimization”.
The static performance analysis technology can be used for architecture exploration of the AI accelerator. The ESL based on virtual platform supports quick simulation for end-to-end AI applications. The neural network compiler provides an deep learning compiler stack for the specific AI accelerators. It aims to close the gap between the productivity-focused deep learning frameworks and the efficiency-oriented accelerator.
Applications & Benefits
The goal is to promote AI chip-horizontal integration for industry cooperation, actively build an industry ecosystem, and grasp business opportunities for AI industrialization.
ITRI is collaborating with worldwide IP/IC vendors to develop a NN compiler to translate the neural network model into codes that can be executed on vendor’s AI SoC hardware.