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工業技術研究院

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技術名稱: 增益型晶圓級晶方尺度構裝技術

技術簡介

‘覆晶封裝技術(Flip Chip technology, FC)需在印刷電路板與電子元件間加入轉接板(substrate),以降低電子元件與基材間因元件操作時發熱或環境變異之熱循環現象所產生之熱應力,因此需在晶粒與基板組裝時增添填膠製程來抒解應力以提高元件可靠性,除此之外,FC另因較細間距及重工性等問題更增加了覆晶技術之成本及應用推廣的阻力。晶圓級構裝技術(WLCSP)可完全解決上述之問題。 電光所開發之增益型晶圓級晶方尺度構裝技術(Enhanced Wafer Level Chip Size Package;e-WLCSP),特色是在晶圓上以製作彈性體(elastomer)的方式作為應力緩衝層(stress buffer layer)來抒解應力,增益了晶圓級晶方尺度構裝(WLCSP)之可靠性,同時,電子所並完成製程改善及效能之提昇,達成真正具備薄型化、堆疊可行性、簡化製程步驟及熱增益型效果之新型態構裝。本技術因採用彈性體製程架構,在晶圓製程即可完成封裝製程,可大幅節省傳統覆晶封裝所需的繁複點膠步驟,並減少封裝後產品面積及體積。

Abstract

‘A high reliable and cost effective wafer level packaging techmology have been developed. Based the innovative patented structure, ERSO demonstrate processing larger die(DNP=6.0mm)both on package amd board level package. To improve the reliablity for lange dies(10 *10mm),a high productivity process for comppliant layer by printing and low coat Ni/Au process for the UBM are achieved. The newly structure is proven as a highly reliable for lange dies and all of them have passed the reliability of compomnt level and board level.

技術規格

‘.Die size:10*10mm .Pitch: 0.8mm, 1.0mm .Solder ball:eutectic @lead free solder .Wafer size: 6" or 8" Si wafer .Design: Fan-in

Technical Specification

‘Die size:10*10mm Pitch: 0.8mm, 1.0mm Solder ball:eutectic @lead free solder Wafer size: 6" or 8" Si wafer Design: Fan-in

技術特色

‘屬晶圓級製程技術具備簡化現有製程複雜性及展現高可靠度之特性, 通過JEDEC Level I procon及JEDEC level III之on board及package type之可靠度測試, 並能進行上板後之重工, 十份適合輕薄短小且高效能之電子產品。

應用範圍

‘晶方尺度構裝技術目前可區分為多種不同之型態,其主要應用領域包含RAM模組(EPROM, SRAM, DRAM)、Flash Memory、DSP、Logic IC、PLD、Analog等多項領域,其市場應用量年複合成長率可達31%以上,並將集中以記憶體為主要應用範圍。電子所開發之e-WLCSP可適用於下一世代之DDR-II記憶體,針對其高速特性(800MHz、1GHz)亦能提供可靠及簡便的封裝型態,且由於晶片製作方式是以整片晶圓來進行,可提供最小的封裝後尺寸及最具潛力的低成本優勢,也因此晶圓級封裝技術未來

接受技術者具備基礎建議(設備)

封裝相關設備

接受技術者具備基礎建議(專業)

具電機電子相關知識

技術分類 製程

聯絡資訊

聯絡人:溫國城 構裝技術組

電話:+886-3-5915654 或 Email:kcwen@itri.org.tw

客服專線:+886-800-45-8899

傳真:+886-3-5820412

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