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工業技術研究院

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技術名稱: 高介電值閘極介電物技術

技術簡介

開發high-k (k>20)閘極介電層之薄膜材料與製程整合技術以符65nm CMOS technology node 及以下元件之需要。

Abstract

High-k (k>20) gate dielectric technology including material, film, and process technology will be developed for the 65nm node and below.

技術規格

高介電常數:k>20,等效厚度小於1.4奈米,漏電流小於氧化矽3個數量級

Technical Specification

High-k constant:k>20, equvilent oxide thickness (EOT)<1.4nm,leakage current<3 orders of oxide

技術特色

利用PVD及AlCVD機台開發高介電閘極介電物,可應用於奈米級電經體,同時可應用在strained Si上,同時利用精密之材料分析儀器如 TEM、XPS、ELLS、MEIS 及電性分析如 Charge Pumping 研究 High-K Stacked Layer

應用範圍

矽半導體之互補式金氧半製程所製作之logic or memory chip

接受技術者具備基礎建議(設備)

具記憶體或foundry能力之半導體廠

接受技術者具備基礎建議(專業)

CMOS製程技術相關元件之設計、製造能力。none

技術分類 製程

聯絡資訊

聯絡人:鍾佩翰 奈米電子技術組

電話:+886-3-5912777 或 Email:stephen.chung@itri.org.tw

客服專線:+886-800-45-8899

傳真:+886-3-5917690

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