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工業技術研究院

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技術名稱: 應變矽CMOS元件與製程技術

技術簡介

在同一世代技術上應變矽CMOS (Strained-Si CMOS)可克服載子移動率劣化的課題,具有提昇性能的特性,主要克服目前技術瓶頸 - 高品質矽鍺虛擬基材的形成技術、全面與局部形變的元件結構設計及製程整合技術,以建立起CMOS製程與元件技術平台,提昇載子移動率和元件效能,使其可應用於高階CMOS SoC產品上。

Abstract

Based on the same technology node, strained-Si CMOS has the advantages of mobility enhancement to overcome the issues of mobility degradation due to scaling down.. To breakthrough the bottlenecks of the strained-Si CMOS technology - high quality SiGe virtual substrate formation and device structure design/integration including global and local strain, the platform of high performance CMOS process/device with mobility enhancement will be developed for the high-end SoC product.

技術規格

矽鍺虛擬基材製程技術開發 - 膜厚 < 1.0um, 線穿缺陷密度 < 104~5/cm2 載子移動率增效 – 電子 > 60%, 電洞> 60%

Technical Specification

SiGe Virtual Substrate – thickness < 1.0um, threading dislocation density < 104~5/cm2 Carrier mobility enhancement – electron > 70%, hole > 60%

技術特色

高品質矽鍺虛擬基材的形成技術 全面與局部形變的元件結構設計及製程整合技術

應用範圍

1.高效能CMOS製程技術 2.高階產品, e.g.: CPU, 繪圖晶片

接受技術者具備基礎建議(設備)

具CMOS元件開發能力之半導體廠

接受技術者具備基礎建議(專業)

CMOS製程技術相關元件之設計、製造能力

技術分類 製程

聯絡資訊

聯絡人:鍾佩翰 奈米電子技術組

電話:+886-3-5912777 或 Email:stephen.chung@itri.org.tw

客服專線:+886-800-45-8899

傳真:+886-3-5917690

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