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工業技術研究院

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技術名稱: 應變矽製程技術

技術簡介

由於在MOS電晶體通道區施予一定大小的應力可增加載子的移動率 (mobility)進而改善元件的輸出特性。本技術利用具離子佈植之氮化矽再搭配晶背高應力層的作用可有效在電晶體通道區產生一定大小的應力進而改善電晶體的特性。

Abstract

The carrier mobility can be enhanced by applying appropriate strain into the channel region of MOS transistors, hence, the output characteristics can be improved. The technique can be used to improve the characteristics of MOS transistors by using ion-implanted silicon nitride and a highly stress layer on the backside of Si substrate.

技術規格

具離子佈植之氮化矽薄膜做為應力源之製程技術- 氮化矽膜厚 < 100nm, 佈植元素為一般半導體常用之元素,可與CMOS製程相容

Technical Specification

Thickness of silicon nitride < 100 nm, implantation species are the usually ones be used in the semiconductor, process can be integrated with CMOS process

技術特色

利用離子佈植技術可產生極大壓縮應力的氮化矽薄膜做為應力源。

應用範圍

MOS或CMOS製程。

接受技術者具備基礎建議(設備)

具MOS或CMOS製程之半導體廠

接受技術者具備基礎建議(專業)

CMOS製程技術相關製造能力。

技術分類 製程

聯絡資訊

聯絡人:鍾佩翰 奈米電子技術組

電話:+886-3-5912777 或 Email:stephen.chung@itri.org.tw

客服專線:+886-800-45-8899

傳真:+886-3-5917690

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