工業技術研究院

技術簡介

H.264是繼MPEG-4之後崛起的另一種新興視訊壓縮技術，其應用領域十分地多元與豐富，包括廣播服務供應商、有線、衛星、電信營運商都對H.264技術充滿了興趣，而隨著HD-DVD撥放機與HDTV的需求在2006年之後的快速起飛，不但為H.264相關產品帶來龐大的商機，更是國際大廠技術角力的重點。 工研院資通所累積多年視訊解碼技術能量，成功研發出具備完整功能的H.264 High Profile解碼器矽智財(Si-Soft Intellectual Property (IP))，並且通過H.264.1規範的High Profile Level 4.1相容性驗證，本矽智財是以專用的硬體電路(fully-hardware-type)來解碼H.264影片，最高可以支援到1920x1088的解析度，而且畫面更新率達到每秒30張循序掃描畫面(progressive)，或是60張交錯畫面(interlaced)，本矽智財可以即時解碼位元率(bitrate)高達50M bps的壓縮影片，完整呈現影片中的高畫質效果。

Abstract

The ITU-T H.264 standard has been developed as the next-generation compression tool for the coding of video content. Many tests have proved that H.264 has provided a factor of two in compression efficiency compared with the existing standards. Additionally, H.264 provides two conceptual layers, namely Video Coding Layer (VCL) and Network Abstraction Layer (NAL), for easily adapting the compressed content to packet-based network. With the flexibility of Soft-IP solution, ITRI can provide the industry with a high efficiency H.264 core technology for digital video, and to help our customers develop competitive time-to-market applications for HDTV.

技術規格

(1) Device: Altera Stratix (2) Speed Grade: -5 (3) Logic Elements: ~ 50,000 (4) Internal Memory: ~ 26,000 Bytes (5) DSP Elements: 20 (6) Timing Constraint for FPGA (7) 352x288 (CIF), 30fps, 2Mbps, YCbCr 420 format (8) Internal memory: 26,000 Bytes (9) Up to 15 reference pictures for H.264 MMCO (10) Passes ITU-T H.264.1 conformance test (11) FPGA-proven Soft Intellectual Property (IP) for easy customization and adaptation to different applications

Technical Specification

(1) Device: Altera Stratix (2) Speed Grade: -5 (3) Logic Elements: ~ 50,000 (30％ for routing interconnects) (4) Internal Memory: ~ 26,000 Bytes (used as RAMs and FIFOs) (5) DSP Elements: 20 (used as 9-bit x 9-bit multipliers) (6) Timing Constraint for FPGA (fmax): 50 MHz lFully-hardware-type decoder, which is compliant to H.264 Baseline Profile, Level 2 for DVB-H CBMS applications (7) Picture resolution: 352x288 (CIF), 30fps, 2Mbps, YCbCr 420 format (8) Internal memory: 26,000 Bytes (9) Up to 15 reference pictures for H.264 Memory Management and Control Operations(MMCO) (10) Passes ITU-T H.264.1 conformance test(bit exactly matching) (11) Module interfaces compliant to Altera Avalon Bus specification and ready to be modified as AMBA compliant signals (12) FPGA-proven Soft Intellectual Property (IP) for easy customization and adaptation to different applications

技術特色

(1) 「純」硬體解碼器: 　　本矽智財是以專用的硬體電路(fully-hardware-type)來解碼H.264影片，不需要高效能的CPU來分擔解碼工作，也就是說外部 CPU只需對解碼器執行：(a)設定參數，(b)下達解碼指令，(c)查詢狀態，即可完成整個解碼流程，如此簡單的hand-shaking可以讓驅動程式的撰寫變得非常容易。 (2) 支援高解析度影片: 　　最高可以支援到1920x1088的解析度，而且畫面更新率達到每秒30張循序掃描畫面(progressive)，或是60張交錯畫面(interlaced)，本矽智財可以即時解碼位元率(bitrate)高達50M bps的壓縮影片，完整呈現影片中的高畫質效果。 (3) 完整支援High Profile所有規範: 　　包含下列解碼工具： 　　　- I/P/B-Slice, Interlaced Picture, 8x8 Intra Prediction, and 8x8 Inverse Transform 　　　- CABAC, Weighted Prediction, and Customized Quantization Matrix 　　　- Picture-level Adaptive Frame-Field (PICAFF) Structure 　　　- Macroblock-level Adaptive Frame-Field (MBAFF) Structure 另外，針對H.264在圖像記憶體管理方面的規範，本矽智財除了支援高達30張的參考圖像外，也完整支援全部的記憶體管理指令(Memory Management and Control Operations (MMCO))，完全不需依賴外部的CPU即可達到高效能的解碼能力。

應用範圍

(1) 高解析度數位電視 (2) DVB-H、PMP、多媒體手機等個人隨身的影音播放裝置 (3) Video Codec相關產品領域

接受技術者具備基礎建議（設備）

(1) IC Design Tools。 (2) FPGA Platform。 (3) Video Codec 相關產品領域。

接受技術者具備基礎建議（專業）

(1) Video Processing. (2) IC Design. (3) Digital Video Coding.

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