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工業技術研究院

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技術名稱: 三維積體電路(3DIC)導通孔(TSV)技術

技術簡介

技術名稱(英文) : 在三維積體電路技術中,導通孔(TSV)是晶片與晶片間互連的最新技術,與以往傳統的IC封裝堆疊技術不同之處是它可以提供三維的垂直導通路徑,並有增加晶片的堆疊密度,提昇產品速度與降低功率消耗,且達到多功能整合等特性。目前工研院的導通孔技術主要分為三個主軸發展:(1) Via-middle技術:把TSV引入於傳統IC製程的前段製程與後段製程之間,並利用後段製程的佈線將TSV連通到元件與訊號源,可提供靈活的整體電路設計度並增進操作表現。(2) Frontside Via-last技術:在傳統IC製程的後段製程完成之後再進行TSV製程,此技法可提供不同應用之各種製造技術以TSV加以整合成為三維晶片。(3) Backside Via-last技術:做完正面之IC製程之後,而從背面將晶圓磨薄之後進行背面的TSV製程,並連接至正面金屬佈線,此技法期望解決在晶圓正面進行TSV製程所可能產生的製程瓶頸,並減少製程成本。

Abstract

TSV process is a new interconnection technology to provide a vertical conduction path among chips. This technology is different from traditional wafer stacking process with wire bond process. The benefits of TSV technology include the increase of chip density and the improvement of product performance. Via-middle technology was introduced into the conventional IC process between FEOL and BEOL, which provide more flexibility to the overall circuit design and enhanced system performance. Frontside via-last technology was introduced once the BEOL of conventional IC process has finished, which integrates various technologies with different applications. Backside via-last technology was used for forming TSV at the wafer backside after the frontside process is complete and wafer backside thinning, which can solve the process issues of frontside TSV and also reduce process cost.

技術規格

‧TSV Via size ≦20um的製程模組開發 ‧Via last製程整合開發。

Technical Specification

‧Process module development of TSV Via size ≦20um ‧Process integration of frontside via-last process

技術特色

利用導通孔之結構,提昇整體電路系統效能,並增加密集度。3DIC技術可藉由晶片堆疊及TSV垂直聯繫訊號的方式使晶片的效能或容量(例如記憶體)持續擴充,因此可以使用原有的technology node來製作晶片並藉由3DIC技術使晶片效能進一步提升。

應用範圍

‧CMOS Image Sensor (CMOS圖像感應器) ‧DRAM (動態記憶體) ‧Non-volatile memory (非揮發性記憶體) ‧RF Chip (射頻晶片) ‧Logic Circuit (邏輯電路)

接受技術者具備基礎建議(設備)

Lithography、Etching、PECVD、PVD、ECD、CMP

接受技術者具備基礎建議(專業)

半導體製程能力、電機、電子、材料、物理等背景

技術分類 製程

聯絡資訊

聯絡人:張順賢 奈米電子技術組

電話:+886-3-5913917 或 Email:shchang@itri.org.tw

客服專線:+886-800-45-8899

傳真:+886-3-5917690

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