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工業技術研究院

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技術名稱: TSV製程開發及整合技術

技術簡介

TSV製程可取代傳統wire-nonding製程,並可增加堆疊的密度及晶片效率,透過垂直的堆疊導通,除了可以縮小晶片體積,增加頻寬,還可以達到節省耗電的效果,其應用包括異質記憶體整合, 3D CIS模組等, 此外新型記憶體整合技術,可以Side-by-side方式連接DRAM及DRAM控制晶片

Abstract

The TSV process is an emerging interconnection technology that will replace the traditional wire-bonding process in chip/wafer stacking. TSV technology can increase chip density and improve product performance. ITRI has developed all of the 3DIC essential enabling technologies and optimized them for different integration scheme requirements. The TSV process is an emerging interconnection technology that will provide a vertical conduction path among chips. This technology is different from the traditional wafer-stacking process with wire bonding. The benefits of TSV technology include increased chip density, smaller form factor, enhanced bandwidth, and reduced power consumption. In ITRI, our 3DIC program aims to develop all the enabling technologies based on the TSV-related process. We have also developed and optimized various integration schemes for different applications. Various test vehicles were adopted for product-level-performance demonstration. These include heterogeneous memory on logic 3D integration, homogeneous memory-to-memory 3D integration, and an ultra-small 3D CIS module. In terms of the memory integration technology, the control chip between DRAMs and be connected by the side-by-side method.

技術規格

12吋矽晶圓的TSV 製程整合開發(Via size≦10um);完成TSV電性量測驗證。

Technical Specification

Via size≦10um

技術特色

提供完整12吋矽晶圓的矽導通孔(TSV)製程,矽導通孔大小5um~30um,矽導通孔深度30um~150um。完成TSV daisy chain的串聯電性量測及製程穩定度驗證。

應用範圍

半導體相關產品(CMOS Image Sensor、DRAM、Non-Volatile Memory、RF Chip、Logic Circuit)

接受技術者具備基礎建議(設備)

Photolithography, DRIE, PECVD, PVD, Electroplating, CMP

接受技術者具備基礎建議(專業)

半導體領域相關人才

技術分類 製程

聯絡資訊

聯絡人:曾育潔 智能應用微系統組

電話:+886-3-5913068 或 Email:jackietseng@itri.org.tw

客服專線:+886-800-45-8899

傳真:+886-3-5917193

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