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工業技術研究院

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技術名稱: 3DIC導通孔製程與整合技術

技術簡介

12吋晶片與底層base晶片堆疊之三維記憶體系統製程整合開發開發,包括光阻在鋁晶片上接著問題之探討與改、SOI IPD電容設計、IPD元件製程開發、晶圓暫時性接合及塗布技術、無凸塊晶圓接合製程整合及電性量測。

Abstract

3D IC Interposer Process and Integration Technology, including the photoresist improvement on the Al pad, SOI IPD capacitor design, IPD component development, temporary bonding and coating, bumpless bonding process and intergration, and electricity test.

技術規格

TSV formation Bump formation Thin wafer handling Stacking ( DRAM + base die) Wafer Size: 12" Wafer thickness > 50 um Cu/Sn microbump Polymer passivation thickness > 4 um

Technical Specification

TSV formation Bump formation Thin wafer handling Stacking ( DRAM + base die) Wafer Size: 12" Wafer thickness > 50 um Cu/Sn microbump Polymer passivation thickness > 4 um

技術特色

3DIC是在晶圓蝕刻出TSV,再填入Via的導電材料如銅、多晶矽、鎢材料形成導電的通道,最後則將晶圓或晶粒薄化再加以堆疊、結合(Bonding),而成為3D IC。 相較於採用Wire Bonding的傳統堆疊封裝,或過去強調效能優勢的SoC設計來說,3D IC的內部連接路徑更短,相對可使晶片間的傳輸速度更快、雜訊更小、效能更佳。 因此,面對長久以來電子產品的需求與發展,始終都是往小型(薄型)化、高度整合、高效率、低成本、低功耗、即時上市(time-to-market)等發展趨勢,3DIC有極佳的優勢。

應用範圍

晶圓代工廠、記憶體製造廠商與半導體封裝廠

接受技術者具備基礎建議(設備)

Lithography、Etching、PECVD、PVD、ECD、CMP

接受技術者具備基礎建議(專業)

CMOS製程技術相關元件之設計、製造能力

技術分類 製程

聯絡資訊

聯絡人:曾育潔 智能應用微系統組

電話:+886-3-5913068 或 Email:jackietseng@itri.org.tw

客服專線:+886-800-45-8899

傳真:+886-3-5917193

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