工業技術研究院

技術簡介

本技術主要內容為批次型超薄鈍化層與摻雜層成膜設備試產機建置及連續性超薄鈍化層與摻雜層太陽電池技術開發。目的是希望藉由本試產機開發鈍化接觸太陽電池關鍵技術並以原有產線小幅修改方式達到加速產業界升級效果，使台灣太陽光電產業跨入下一世代太陽電池技術。由研發結果發現，此二合一的批次型超薄鈍化層與摻雜層成膜設備是可行的設計，薄膜品質可達到Rsh≦200Ω/sq，J0≦20fA/cm2。

Abstract

The main contents of this report are regarding to the installation of a batch-type pilot production machine which is used for the depositions of ultra-thin passivation layer and doping layer, and also the solar cell technology development by using successive depositions of ultra-thin passivation layer and doping layer. We are aiming to develop some key technologies for passivation contact solar cells by using this pilot production machine, and hopefully by small-scale change of existing production line to accelerate the upgrade of Taiwanese solar cell industry towards next generation solar cell technology. According to our research results, it is a feasible design for the two-in-one batch-type depositions of ultra-thin passivation layer and doping layer, as the thin film qualities are confirmed with Rsh≦200Ω/sq and J0≦20fA/cm2.

技術規格

1. 多晶矽厚度均勻性(目標值：100nm)：M2尺寸晶片5點的均勻性要＜10％；Wafer to Wafer的均勻性要＜10％；Run to Run的均勻性要＜3％(以100nm)。 2. 多晶矽片阻值均勻性(以100nm厚度下量測)：M2尺寸晶片5點的均勻性要＜8％；Wafer to Wafer的均勻性要＜10％；Run to Run的均勻性要＜3％。 3. 電性驗證(iVoc及J0) (以多晶矽100nm)：三次重覆驗證，36片中至少需有90％的iVoc大於730mV，J0＜4fA。 4. 溢鍍(Wrap around)：三次重覆驗證，至少進行72片(24片x3)測試，在多晶矽厚度為250nm的條件下，溢鍍至另一面的晶片邊緣深度＜ 5mm。

Technical Specification

1. Polysilicon thickness uniformity (target value: 100nm): the uniformity of M2 size wafers at 5 points should be ＜10％; the uniformity of wafer to wafer should be ＜10％; the uniformity of Run to Run should be ＜3％ (at 100nm) ). 2. Polysilicon sheet resistance uniformity (measured at a thickness of 100nm): the uniformity of M2 size wafers at 5 points must be ＜8％; the uniformity of wafer to wafer must be ＜10％; the uniformity of run to run must be ＜3 ％. 3. Electrical verification (iVoc and J0) (using polysilicon 100nm): Three repeated verifications, at least 90％ of the 36 cells must have iVoc greater than 730mV and J0＜4fA. 4. Wrap around : three repeated verifications, at least 72 pieces (24 pieces x3) test, under the condition of polysilicon thickness of 250nm, the edge depth of the wrap around to the other side of the wafer ＜5mm.

技術特色

1. 技術已達少量試產及量產驗證階段。 2. 將超薄穿隧氧化層成長及摻雜多晶矽沉積製程整合於單一爐管之中，以降低製程時間。 3. 可以用作n型太陽能電池及p型太陽能電池的背面鈍化接觸。 4. 在鈍化接觸接面處具有高度的載子選擇性，大幅降低電子-電洞對的復合電流。

應用範圍

光電、半導體，能源等需薄膜製程相關產業。

接受技術者具備基礎建議（設備）

光電製造，生產，化學氣相沉積等相關設備。

接受技術者具備基礎建議（專業）

具備微電子、半導體、光電、能源、研發工程人員與銷售業務。

聯絡資訊