服務說明
工研院晶片布局設計服務團隊，累積豐富IC設計流程經驗，運用專業知識及EDA工具提供Automatic Placement and Routing, Static Timing Analysis, Formal verification, Physical verification等服務項目。
Design In & Out Data
IN (From Designer)
- RTL and constraints
- Synthesized Netlist (w | w/o dft design)
- Custom IP data (GDS / LEF / LIB / DB are required) can be frame only
- Scan DEF
- Power Format (UPF)
- Misc requirement (don’t touch / keepout / Floorplan guide …)
OUT
- GDS / DEF / SPI
- Post-APR netlist / SPEF / UPF for STA / Formal / Post-sim
- STA / Formal / DRC / ANT / LVS… report
【聯絡窗口】