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Industrial Technology Research Institute

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Wafer-Level Memory Stacking Applications

Technology Overview

Wafer-Level Memory Stacking Applications.
Wafer-Level Memory Stacking Applications.

In order to strengthen global competitiveness of the memory industry in Taiwan, ITRI has developed Si interposers with Through-Silicon Vias (TSVs) technology for the double stack architecture of dynamic random access memory (DRAM), and an oxide-to-oxide wafer bonding technology was established and verified with real DRAM wafers. This technology can meet the memory packaging requirements for higher capacity, higher performance, lower power consumption, lower latency, and smaller volume. This technology has passed the open/short, leakage current and functional tests, and the yield before and after the stacking processes is almost the same. The confirmed thickness of finished top wafer has been reduced to 20 μm, successfully verifying manufacturing feasibility.

Applications & Benefits

This technology can meet the memory packaging requirements for higher capacity, higher performance, lower power consumption, lower latency, and smaller volume.