Technology Overview
Low Temperature Wafer-Level Hybrid Bonding Technology.
Heterogeneous integration packaging has become the core technology for chiplet packaging. Its development aims to support high-bandwidth and high-speed computing in various application domains, including smartphones, HPC, AI, and more.
As the density of switching elements within chips increases, the diameter of copper interconnects needs to be continually reduced. To overcome the limitations posed by the miniaturization of solder bump sizes and their higher resistance, direct metal bonding and hybrid bonding techniques have emerged as key breakthroughs in next-generation heterogeneous integration.
The process involves achieving wafer-level, low-temperature hybrid bonding with line-widths and line-spacing of 2 micrometers. This bonding process is conducted at 150 degrees Celsius and under a pressure of 1.06 MPa for one hour to complete the bonding process. Wafer-level hybrid bonding at low temperatures enables the realization of heterogeneous integration, combining memory (DRAM) and logic chips, among others, in a multi-chip heterogeneous integration architecture.
Applications & Benefits
- The multi-chip heterogeneous integration architecture, combining memory (DRAM) and logic chips, is implemented through wafer-level hybrid bonding on either homogeneous or reconstituted wafers.
- Wafer-level bonding over large areas reduces process time and costs.
- Precise bonding with fine line structure enhances the interconnect density to over 40,000 I/O/mm².
＜111＞nc-Cu Bond Pad & Hybrid Bonding.
Low Temperature Wafer-Level Hybrid Bonding Technology.