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Industrial Technology Research Institute


Heterogeneous Integration with Through Silicon via Technology

Technology Overview

The TSV process is a key technology for 3D chip stacking by providing a route with the shortest and vertical interconnection path to replace the traditional wire-bonding process in chip/wafer stacking. Due to its vertical interconnection, the TSV technology can increase chip density, reduce form factor, enhance bandwidth, cut power consumption, and improve product performance. At ITRI, our 3DIC program aims to develop all the enabling technologies based on the TSV-related process. We have also developed and optimized various integration schemes for different applications.

Applications & Benefits

ITRI has successfully applied the backside via last TSV integration flow (with 5μm TSV diameter and 50μm depth) in the stacking scheme of SRAM and logic chips to significantly increase the system performance by more than 60% and cut the power consumption by more than 70%. This technology will also be adopted in the next generation memory architecture development collaboration project with foreign companies to fabricate memory cubes with high performance and low power consumption.

ITRI also collaborated with domestic memory chip makers to successfully stack 4-layer DDR3 chips together with 8Gb capacity chips by adopting the via middle TSV technology. To further shrink the chip area, improve system performance, consume less power, and reduce manufacture cost of the TSV technology, the TSV integration process with 3μm TSV diameter and 30μm depth has also been developed successfully in ITRI.

Heterogeneous Integration with Through Silicon via Technology.
Heterogeneous Integration with Through Silicon via Technology.

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